An integrated circuit such as a system-on-a-chip (SoC) often includes sub-systems such as receivers and transmitters that are clocked by corresponding clock signals. To keep the various sub-systems synchronized, it is conventional for an SoC to include a reference clock transmitter that provides a reference clock to a plurality of PLLs. Each PLL provides an output clock signal to a corresponding subsystem. An example clock distribution architecture for an SoC 100 is shown in FIG. 1. SoC 100 includes a plurality of n sub-systems ranging from a first sub-system 105, followed by a second sub-system 110, and so on to a final nth sub-system 115. Each sub-system is clocked by a corresponding clock signal. First sub-system 105 is thus clocked by a first clock signal clk1, second sub-system 110 is clocked by a second clock signal clk2 and so on such that nth sub-system 115 is clocked by an nth clock signal clkn. Each clock signal is produced by a fractional-N PLL. A first fractional-N PLL (PLL1) produces the first clock signal clk1, a second fractional-N PLL (PLL2) produces the second clock signal clk2, and so on such that an nth fractional-N PLL (PLL_n) produces the nth clock signal clkn. Each fractional-N PLL produces its clock signal responsive to a reference clock signal Fref from a reference clock source 120 such as a crystal oscillator.
The use of fractional-N PLLs in SoC 100 provides greater flexibility with regard to the frequency for the clocking of the sub-systems. In contrast, the clock frequency from an integer-N PLL has an integer relationship to the reference clock. But a fractional-N PLL untethers the sub-system clocking from such an integer relationship so that the sub-system clock frequencies can have a non-integer relationship to the reference clock. Although fractional-N PLLs thus provide advantageous frequency flexibility, their usage introduces a phase ambiguity between the various sub-system clocks. In particular, it is conventional for each fractional-N PLL to be shut down while the corresponding sub-system is in a dormant or sleep mode of operation to enable low-power operation of SoC 100. Each fractional-N PLL thus operates only when enabled such as commanded through a multi-bit enable signal 125. Due to the fractional division in the fractional-N PLLs, the clocking frequencies for the sub-systems will have a phase relationship that varies depending upon when a particular sub-system was enabled. This random phase relationship is problematic in a number of applications. For example, in the uplink and downlink during multiple-input-multiple-output (MIMO) operation, a known phase relationship avoids unnecessary channel estimations. Moreover, undesirable couplings between the sub-systems may be minimized through an optimal phase relationship for the sub-system clocking. In addition, cross-clock domain data and signal handover is simplified when the sub-system clocking has a known phase relationship.
Accordingly, there is a need in the art for a clock phase management in which the output clock signals from fractional-N PLLs have a known phase relationship.